B. Kuo, “Floating-Muscles Kink-Impact Related Capacitance Behavior out-of Nanometer PD SOI NMOS Gadgets” , EDMS , Taiwan

B. Kuo, “Floating-Muscles Kink-Impact Related Capacitance Behavior out-of Nanometer PD SOI NMOS Gadgets” , EDMS , Taiwan

71. Grams. S. Lin and you may J. B. Kuo, “Fringing-Caused Slim-Channel-Impression (FINCE) Associated Capacitance Behavior out-of Nanometer FD SOI NMOS Products Playing with Mesa-Separation Thru 3d Simulator” , EDSM , Taiwan ,

72. J. B. Kuo, “Advancement out of Bootstrap Techniques in Lower-Voltage CMOS Electronic VLSI Circuits to have SOC Apps” , IWSOC , Banff, Canada ,

P. Yang, “Door Misalignment Impact Associated Capacitance Decisions off a great 100nm DG FD SOI NMOS Product having n+/p+ Poly Most useful/Bottom Entrance” , ICSICT , Beijing, China

73. Grams. Y. Liu, Letter. C. Wang and J. B. Kuo, “Energy-Productive CMOS Large-Load Rider Circuit towards Subservient Adiabatic/Bootstrap (CAB) Technique for Low-Power TFT-Lcd Program Programs” , ISCAS , Kobe, The japanese ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you may K. W. Su, “CGS Capacitance Sensation out-of 100nm FD SOI CMOS Products with HfO2 High-k Entrance Dielectric Offered Vertical and Fringing Displacement Effects” , HKEDSSC , Hong kong ,

75. J. B. KUo, C. H. Hsu and C. P. Yang, “Gate-Misalignment Relevant Capacitance Behavior of a beneficial 100nm DG SOI MOS Devices that have N+/p+ Top/Bottom Gate” , HKEDSSC , Hong-kong ,

76. G. Y. Liu, N. C. Wang and you may J. B. Kuo, “Energy-Successful CMOS High-Load Driver Circuit on Complementary Adiabatic/Bootstrap (CAB) Technique for Lower-Power TFT-Liquid crystal display Program Applications” , ISCAS , Kobe, Japan ,

77. H. P. Chen and you will J. B. Kuo, “A great 0.8V CMOS TSPC Adiabatic DCVS Reason Routine towards Bootstrap Technique to own Reduced-Fuel VLSI” , ICECS , Israel ,

B. Kuo, “A novel 0

80. J. B. Kuo and you can H. P. Chen, “A reduced-Voltage CMOS Load Rider toward Adiabatic and Bootstrap Suggestions for Low-Fuel Program Applications” , MWSCAS , Hiroshima, The japanese ,

83. M. T. Lin, E. C. Sunlight, and J. B. Kuo, “Asymmetric Door Misalignment Effect on Subthreshold Characteristics DG SOI NMOS Gizmos Offered Fringing Digital Field effect” , Electron Gadgets and Thing Symposium ,

84. J. B. Kuo, Elizabeth. C. Sunrays, and Yards. T. Lin, “Investigation off Gate Misalignment Effect on the Endurance Voltage out of Twice-Entrance (DG) Ultrathin FD SOI NMOS Devices Using a tight Model Offered Fringing Electric Field-effect” , IEEE Electron Products to possess Microwave Jeg tenkte pГҐ dette oven and you will Optoelectronic Apps ,

86. E. Shen and you will J. 8V BP-DTMOS Stuff Addressable Thoughts Cell Circuit Based on SOI-DTMOS Techniques” , IEEE Conference towards the Electron Equipment and Solid-state Circuits , Hong-kong ,

87. P. C. Chen and you can J. B. Kuo, “ic Reason Circuit Using a direct Bootstrap (DB) Way of Low-voltage CMOS VLSI” , Global Symposium on Circuits and you may Expertise ,

89. J. B. Kuo and you may S. C. Lin, “Lightweight Dysfunction Design to possess PD SOI NMOS Devices Offered BJT/MOS Impression Ionization to possess Liven Circuits Simulation” , IEDMS , Taipei ,

90. J. B. Kuo and you may S. C. Lin, “Compact LDD/FD SOI CMOS Unit Design Given Opportunity Transport and you may Self Heating having Liven Circuit Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you will J. B. Kuo, “Fringing-Created Burden Reducing (FIBL) Effects of 100nm FD SOI NMOS Gadgets with high Permittivity Gate Dielectrics and you may LDD/Sidewall Oxide Spacer” , IEEE SOI Conference Proc , Williamsburg ,

ninety five. J. B. Kuo and S. C. Lin, “The latest Fringing Electric Field effect with the Brief-Channel Effect Tolerance Voltage out of FD SOI NMOS Equipment which have LDD/Sidewall Oxide Spacer Structure” , Hong-kong Electron Gadgets Fulfilling ,

93. C. L. Yang and you will J. B. Kuo, “High-Heat Quasi-Saturation Brand of Highest-Voltage DMOS Fuel Equipment” , Hong-kong Electron Devices Conference ,

94. Age. Shen and you may J. B. Kuo, “0.8V CMOS Posts-Addressable-Thoughts (CAM) Cellphone Ciurcuit which have an instant Mark-Examine Capability Having fun with Most PMOS Active-Endurance (BP-DTMOS) Method Based on Simple CMOS Technical getting Lowest-Current VLSI Options” , Around the globe Symposium to the Circuits and Assistance (ISCAS) Proceedings , Washington ,

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